1. Field of the Invention
The present invention relates to a lateral MOSFET having a trench gate structure and a manufacturing method thereof.
2. Description of Related Art
There is proposed a lateral MOSFET having a trench gate structure as a structure to lower ON resistance by increasing a channel width without increasing an area of an element.
A structure of one example of the lateral MOSFET having a prototype trench gate structure is shown in FIGS. 7A, 7B, 8A, and 8B.
FIG. 7A is a plan view, and FIG. 7B is a perspective view showing a shape of a trench. FIG. 8A is a cross sectional view taken along the line IIXA-IIXA in FIG. 7A. FIG. 8B is a cross sectional view taken along the line IIXB-IIXB in FIG. 7A. FIG. 7A does not include a surface electrode.
In FIGS. 7A, 7B, 8A, and 8B, a prototype lateral MOSFET 10 has a p-type substrate 11, an n-type high-resistance layer 12, a p-type well layer 13, an n-type source layer 14, an n-type drain layer 15, a trench 16, a gate insulation film 17, a gate electrode 18, a source electrode 19, and a drain electrode 20.
The lateral MOSFET 10 has the n-type high-resistance layer 12 formed on the p-type substrate 11.
The stripe-shaped p-type well layer 13 is selectively formed in a predetermined area of the n-type high-resistance layer 12.
The stripe-shaped n-type source layer 14 is selectively formed in a predetermined area in the p-type well layer 13.
The stripe-shaped n-type drain layer 15 is selectively formed in a predetermined area in the n-type high-resistance layer 12 at a position spaced apart from the p-type well layer 13 so as to be parallel to the n-type source layer 14.
In the intermediate region extending from the end portion of the n-type drain layer 15 to the n-type high-resistance layer 12, the p-type well layer 13, and the end portion of the n-type source layer 14, a plurality of trenches 16 are formed extending through the p-type well layer 13 to an intermediate depth of the n-type high-resistance layer 12.
Further, the trenches 16 each have a stripe-like planar shape perpendicular to the n-type source layer 14 and the n-type drain layer 15 and are disposed in parallel to one another.
Further, in the intermediate region between the n-type source layer 14 and the n-type drain layer 15 and in the respective trenches 16, the gate electrode 18 composed of polycrystalline silicon is formed through the gate insulation film 17.
The source electrode 19 is formed on the n-type source layer 14, and the drain electrode 20 is formed on the n-type drain layer 15.
In such a lateral MOSFET 10, if a gate voltage is made larger than the threshold value voltage while applying the predetermined voltage between drain and source, then the p-type well layer 13 which is faced to the gate electrode 18 is inverted into the n conductivity type, so as to form the channel ch (see an area shown in oblique line in FIG. 8B).
Then electrons e are injected from the n-type source layer 14 into the n-type drain layer 15 through the channel ch.
The channel ch is formed not only on the substrate surface but also in a depth direction along with the side surface of the trench 16, which makes it possible to increase the channel width (for example, see FIGS. 1 and 2 of Japanese Unexamined Patent Application Publication No. 11-103058).
Now, a method of forming the trench 16 of the lateral MOSFET 10 will be described. A high-concentration layer including the n-type source layer 14 and the n-type drain layer 15 is formed in a predetermined area. Then a resist mask (not shown) is formed on the substrate. The resist mask has an opening where the trench 16 will be formed. Then an anisotropic etching is performed straightforward to the predetermined depth so as to form the trench 16 having a rectangular cross sectional shape as shown in FIG. 7B.
However, in the lateral MOSFET 10 which is described above, entire channel ch in a depth direction along the side surface of the trench 16 can not effectively contribute to the flow of electrons e.
This is because the depths of the n-type source layer 14 and the n-type drain layer 15 are shallow with respect to the depth of the trench 16 even if the channel ch is formed in the depth direction in the prototype lateral MOSFET. In such a case, instead of bypassing the gate electrode in the depth direction, almost all the electrons e flow in the vicinity of the substrate surface almost linearly from the n-type source layer 14 toward the n-type drain layer 15 as shown in FIG. 8B.
To overcome the above problem, there is proposed a configuration for making the depths of the n-type source layer and the n-type drain layer deeper than the depth of the trench as shown in FIGS. 9A and 9B as a second prototype example.
FIG. 9A is a plan view and FIG. 9B is a cross sectional view taken along the line IXB-IXB in FIG. 9A. FIG. 9A does not include a surface electrode.
In FIGS. 9A and 9B, another prototype lateral MOSFET 30 has a high-resistance semiconductor substrate 1, a gate electrode 3, an n-type source layer 4, an n-type drain layer 5, agate insulation film 6, a p-type well layer 7, and a trench 8.
In such a lateral MOSFET 30, the n-type source layer 4 and the n-type drain layer 5 are deeply formed as shown in FIG. 9B. Therefore, the channel ch formed in the depth direction along the side surface of the trench 8 effectively contributes to the flow of electrons e.
Note that the method of obliquely implanting ion from the side surface of the trench 8 is employed to form the deeper n-type source layer 4 and the n-type drain layer 5 so as to secure uniformity of ion concentration distribution in the depth direction (see for example FIGS. 1A and 1C of Japanese Unexamined Patent Application Publication No. 2006-19518).
Although the effective channel width is supposed to be increased as the depths of the n-type source layer 4 and the n-type drain layer 5 are increased along with the depth of the trench 8 in such a lateral MOSFET 30, there is a limit in this depth due to reasons as follows.
The first reason is that an incident angle θ of the oblique ion implantation becomes smaller as the depths of the n-type source layer 4 and the n-type drain layer 5 are increased in order to increase the channel width. For example, if the incident angle of the oblique ion implantation θ is 30°, the incident angle to the trench side surface (vertical surface) θV is 60° whereas the incident angle to the substrate surface (horizontal surface) θH is 30° as shown in FIG. 10. Therefore, there is a large difference between two incident angles.
As a result, the thickness (t2) of the high-concentration layer formed in the trench side surface (vertical surface) is made thinner compared with the thickness (t1) of the high-concentration layer formed on the substrate surface (horizontal surface), which means t2<t1. Therefore, even when the channel ch is formed in the depth direction, electrons e are not fully supplied from the high-concentration layer or the supplied electrons are made non-uniform, which means the channel ch in the depth direction cannot effectively be used.
The second reason is that there is a limit in the trench depth when there is a buried oxide film such as an SOI substrate (not shown) in the substrate. In such a case, the channel width cannot further be increased.
One object of the present invention is to provide a lateral MOSFET having a trench gate structure and the manufacturing method thereof, thereby making it possible to secure the thicknesses of the source layer and the drain layer deeply formed along the trench and to obtain the wider channel width resulting in decreasing ON resistance.